High-performance Digital Signal Processors (DSPs), such as the DSP16210 manufactured by the assignee of this application, frequently need to fetch from memory a number of data units such as a doubleword (two sequential words) in a given instruction cycle. Given a starting address of, for example, a doubleword, a memory access system must attempt to access both the word residing at the starting address and the word residing at the next sequential address in a single instruction cycle. If the starting address is even, the access is said to be aligned. If the starting address for a given access is odd, the access is said to be misaligned.
FIG. 1 is a block diagram of a conventional interleaved memory access system. A data bus supplies 32 bits of write data to the write data alignment logic, which separates the 32 bits of data into 16 bits of data directed to an even memory bank RAME and 16 bits of data directed to an odd memory bank RAMO. Within the memory banks RAME and RAMO, individual locations are selected by address bus signals A[10:1], and the memory banks RAME and RAMO are selected for operation by an ENABLE signal. For read operations, the memory banks RAME and RAMO each provide 16 bits of data to the read data alignment logic. The address bus signal A[0] is used to select between the memory banks RAME and RAMO.
When the starting address is even and the access is aligned, standard low-order memory interleaving techniques permit access to both the first and the second words in the same instruction cycle. Such standard techniques decode the starting address to select a given row in both an even and an odd memory bank. For an aligned access with the starting address being even, the even memory bank provides the first word and the odd memory bank provides the second word, and both of the words reside in the selected row. Thus, for aligned accesses both words are accessed in the same instruction cycle.
For a mis-aligned access with the starting address being odd, standard low-order memory interleaving techniques typically cannot access both the first and the second words in the same instruction cycle. When the starting address is odd, the odd memory bank provides the first word, and the even memory bank provides the second word. However, when the starting address is odd, the row of the memory banks selected by decoding the starting address contains only the first word in the odd memory bank. The second word resides in the even memory bank at the next sequential address, which is in the next sequential row. Since conventional interleaved memory systems cannot typically enable and access two different rows in the same instruction cycle, a second instruction cycle is necessary to access the second word in the even memory bank. These additional instruction cycles slow memory accesses and degrade overall system performance.
FIGS. 2 and 3 are block diagrams of conventional interleaved memory systems. FIG. 2 shows an even memory bank mapped to the address range 0.times.07fe:0.times.0000, while FIG. 3 shows a corresponding odd memory bank mapped to the address range 0.times.07ff:0.times.0001. The problem of conventional RAM address decoding may be illustrated by considering an example of a mis-aligned doubleword access. For example, consider a mis-aligned doubleword access with a starting address of 0.times.0003. The memory access system must access the first word residing at the odd address 0.times.0003 and the second word residing at the even address 0.times.0004. In FIG. 3, the odd first address 0.times.0003 decodes to row 0, column 1. In FIG. 2, the even second address 0.times.0004 decodes to row 0, column 2. Because 0.times.0003 and 0.times.0004 decode to different storage locations in different rows and columns in the even and odd memory banks, the memory access system of FIGS. 2 and 3 must run a second cycle to access the second word, and thus cannot typically service a mis-aligned doubleword access in a single memory access.
In contrast, referring to FIGS. 2 and 3, for an aligned doubleword access with an even starting address of 0.times.0002, the even memory bank in FIG. 2 decodes 0.times.0002 to select row 0, column 1. The odd memory bank in FIG. 3 decodes the odd address 0.times.0003 to select the same row and column. Because both memory banks decode the same row and column, the memory access system of FIGS. 2 and 3 can typically access both words of an aligned access in a single cycle.
There are several solutions to the above shortcomings of conventional memory address decoding for mis-aligned accesses. One approach is to employ a look-ahead buffer and pre-fetch misaligned data into that buffer, thereby priming that buffer with the data that might later be sought through misaligned memory accesses. However, this approach suffers several disadvantages, including the additional hardware required to support the buffer, the additional instruction cycles required to load the buffer, the processing overhead required to maintain the integrity of the buffer with respect to the external memory.
Another approach is to ensure that code fetches, as opposed to data fetches, are always aligned, thereby at least optimizing code fetches. The costs of this approach are more complicated code fetching logic and an extra clock delay required for code branches to odd addresses as compared to even addresses.
Accordingly, there is a need in the art for a memory access system and method that supports misaligned accesses, preferably providing single-cycle access to two sequential data units, such as a doubleword comprising two consecutive words, when the starting address is odd. It is an objective of the present invention to provide such a system and method.